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INTEGRATED CIRCUITS
DATA SHEET
SAA5249 Integrated VIP and Teletext with Background Memory Controller (IVT1.1BMCX)
Preliminary specification Supersedes data of December 1993 File under Integrated Circuits, IC02 1996 Nov 07
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
FEATURES * Complete teletext decoder featuring a background memory controller in a single 48-pin DIP package. Capable of storing of up to 512 teletext pages in an external DRAM, giving instant access to the teletext data * Automatic processing of extension packet 26 for widest possible language decoding. All our standard language options can be available, and the language option is readable via I2C-bus. * 100% hardware compatible with the SAA5247 plug-in replacement and with the possibility of extra market in those countries with packet 26 transmissions. Still pin-aligned to SAA5254 and SAA5244A. * 100% software compatible with the SAA5247, and SAA5244A, except if the special OSD symbols were used. Also 100% software compatible to SAA5254. In all events there is a change to the ROM ID number. * The device is pin-aligned with the other members of the new Philips teletext decoder family, i.e. SAA5281 and the SAA5254, making one hardware solution for the whole range * Low software overhead for the microprocessor * RGB interface to standard colour decoder ICs, push-pull output drive. QUICK REFERENCE DATA SYMBOL VDD IDD Vsyn Vvid fXTAL Tamb supply voltage supply current sync amplitude video amplitude crystal frequency operating ambient temperature PARAMETER - 0.1 0.7 - -20 MIN. 4.5 TYP. 5.0 90 0.3 1.0 27 - GENERAL DESCRIPTION
SAA5249
The Integrated VIP and Teletext (IVT1.1BMCX) is a teletext decoder (contained within a single chip package) for decoding 625-line based World System Teletext transmissions. With its built-in background memory controller the device can store incoming teletext packets in the external 1M4 DRAM. With this large packet store which can be rapidly scanned, we can achieve near instantaneous access to all the pages transmitted by the broadcaster. This version of the decoder also contains some extra hardware to process extension packet 26 automatically, extending the markets to which the TV chassis can be shipped and offering many more language options for the set maker.
MAX. 5.5 120 0.6 1.4 - +70 V
UNIT mA V V MHz C
ORDERING INFORMATION TYPE NUMBER SAA5249P/E SAA5249GP/E PACKAGE NAME DIP48 QFP64 DESCRIPTION plastic dual in-line package; 48 leads (600 mil) plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height VERSION SOT240-1 SOT319-1
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
BLOCK DIAGRAM
SAA5249
A0 to A9
handbook, full pagewidth
D0 to D3 4
R/W
CAS0
CAS1 RAS
Y
BLANK
COR
RGBREF R/G/B 3
ODD/EVEN
10 46 45
42 SEL1 SEL2
23
24
41
29
21
27 DISPLAY
20
17 to 19
28
DRAM INTERFACE
VDD1 VDD2 VSSn
3
12 16, 22 38
SAA5249
BACKGROUND MEMORY CONTROL
HAMMING CHECKER AND PACKET 26 PROCESSING ENGINE
MUX DATA SLICER AND CLOCK REGENERATOR
TELETEXT ACQUISITION AND DECODING
PAGE MEMORY
31 DCVBS VSS1 REF+ 7 8 ANALOG TO DIGITAL CONVERTER I 2C - BUS INTERFACE TIMING CHAIN 30
SDA SCL
OSCOUT OSCIN
4 5 CRYSTAL OSCILLATOR
INPUT CLAMP AND SYNC SEPARATOR 9 11 10 CVBS 13 POL 15
DISPLAY CLOCK PHASE LOCKED LOOP
6 GNDO
14 STTV/LFB
MLB304
BLACK IREF
VCR/FFB
Fig.1 Block diagram for SOT240-1 (DIP48) package.
1996 Nov 07
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
PINNING PIN SYMBOL SOT240-1 n.c. n.c. VDD1 OSCOUT OSCIN GNDO VSS1 REF+ BLACK CVBS IREF VDD2 POL STTV/LFB VCR/FFB VSS2 REF- R G B RGBREF BLANK VSS3 CAS0 CAS1 A4 A3 COR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 SOT319-1(1) 1 2 25 27 28 29 12 32 35 36 37 38 39 40 42 30 31 49 50 51 52 53 54, 55 56 57 58 59 60 not connected not connected +5 V supply 27 MHz crystal oscillator output 27 MHz crystal oscillator input 0 V crystal oscillator ground 0 V ground DESCRIPTION
SAA5249
positive reference voltage; this pin should be connected to ground via a 100 nF capacitor video black level storage pin; this pin should be connected to ground via a 100 nF capacitor composite video input pin; a positive-going 1 V (p-p) input is required, connected via a 100 nF capacitor reference current input pin; connected to ground via a 27 k resistor +5 V supply STTV/LFB/FFB polarity selection pin sync to TV output pin/line flyback input pin; function controlled by an internal register bit (scan sync mode) PLL time constant switch/field input pin; function controlled by an internal register bit (scan sync mode) 0 V ground negative reference voltage; this pin should be connected to REF+ via a 100 nF capacitor dot rate character output of the RED colour information dot rate character output of the GREEN colour information dot rate character output of the BLUE colour information input DC voltage to define the output high level on the RGB pins dot rate fast blanking output 0 V ground; internally connected for SOT319 column address select to external DRAM for BMCX function column address select to external DRAM for BMCX function for second DRAM where two 256 k x 4 devices are used address output to external DRAM for BMCX function address output to external DRAM for BMCX function programmable output to provide contrast reduction of the TV picture for mixed text and picture displays or when viewing newsflash/subtitle pages; open drain output 25 Hz output synchronized with the CVBS input field sync pulses to produce a non-interlaced display by adjustment of the vertical deflection currents
ODD/EVEN
28
61
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
PIN SYMBOL SOT240-1 Y SCL SDA A5 A2 A6 A1 A7 A0 VSS4 A8 A9 RAS R/W D2 D0 SEL2 SEL1 D3 D1 Note 1. The remaining pins for SOT319 are not connected. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SOT319-1(1) 62 63 64 4 5 6 8 9 11 43 13 14 15 18 19 20 21 22 23 24 DESCRIPTION
SAA5249
dot rate character output of teletext foreground colour information; open drain output serial clock input for I2C-bus; it can still be driven HIGH during power-down of the device serial data port for the I2C-bus; open drain output. It can still be driven HIGH during power-down of the device address output to external DRAM for BMCX function address output to external DRAM for BMCX function address output to external DRAM for BMCX function address output to external DRAM for BMCX function address output to external DRAM for BMCX function address output to external DRAM for BMCX function 0 V ground address output to external DRAM for BMCX function address output to external DRAM for BMCX function row address select to external DRAM read/write for external DRAM data input/output for external DRAM data input/output for external DRAM RAM select input to choose external DRAM size RAM select input to choose external DRAM size data input/output for external DRAM data input/output for external DRAM
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SAA5249
n.c. n.c. VDD1 OSCOUT OSCIN GNDO VSS1 REF BLACK
1 2 3 4 5 6 7 8 9
48 47 46 45 44 43 42
D1 D3 SEL1 SEL2 D0 D2 R/W
41 RAS 40 A9 39 A8 38 VSS4 37 A0 SAA5249P 36 A7
CVBS 10 IREF 11 VDD2 12 POL 13 STTV/LFB 14 VCR/FFB 15 VSS2 16 R 17 G 18 B 19 RGBREF 20 BLANK 21 VSS3 22 CAS0 23 CAS1 24
MLB305
35 A1 34 A6 33 A2 32 A5 31 SDA 30 SCL 29 Y 28 ODD/EVEN 27 COR 26 A3 25 A4
Fig.2 Pin configuration; SOT240-1 (DIP48).
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SAA5249
61 ODD/EVEN
62 Y
index corner
52 RGBREF 51 B 50 G 49 R 48 47 46 45 44 43 VSS4 n.c. 42 VCR/FFB 41 n.c. 40 STTV/LFB 39 POL 38 VDD2 37 IREF 36 CVBS 35 BLACK 34 n.c. 33 n.c. 32 REF
MLB306
55 V SS3
54 V SS3 V SS2 30
n.c. n.c. n.c. A5 A2 A6
1 2 3 4 5 6
n.c. 7 A1 A7 8 9 SAA5249GP
n.c. 10 A0 11 VSS1 12 A8 13 A9 14 RAS 15 n.c. 16 n.c. 17 R/W 18 D2 19 D0 20 SEL2 21 SEL1 22 D3 23 D1 24
VDD1 25
n.c. 26
OSCOUT 27
OSCIN 28
GNDO 29
Fig.3 Pin configuration; SOT319-1 (QFP64).
1996 Nov 07
7
REF
31
53 BLAN
57 CAS1
56 CAS0
60 COR
64 SDA
63 SCL
59 A3
58 A4
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI VO IO IIOK Tamb PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current operating ambient temperature MIN. -0.3 -0.3 -0.3 - - -20
SAA5249
MAX. +6.5 VDD + 0.5 VDD + 0.5 10 20 +70 V V V
UNIT
mA mA C
QUALITY AND RELIABILITY This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E". The principal requirements are shown in Tables 1 to 4.
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Group A Table 1 Acceptance tests per lot TEST Mechanical Electrical Group B Table 2 Processability tests (by package family) TEST Solderability Mechanical Solder heat resistance Group C Table 3 Reliability tests (by process family) TEST Operational life Humidity life CONDITIONS 168 hours at Tj = 150 C temperature, humidity, bias (1000 hours, 85 C, 85% RH or equivalent test) Tstg(min) to Tstg(max) <7% LTPD <15% LTPD <15% LTPD REQUIREMENTS(1) REQUIREMENTS(1) cumulative target: <100 ppm cumulative target: <100 ppm
SAA5249
REQUIREMENTS(1) <1500 FPM; equivalent to <100 FITS at Tj = 70 C <2000 FPM
Temperature cycling performance Table 4
<2000 FPM
Reliability tests (by device type) TEST CONDITIONS ESD Human body model 2000 V, 100 pF, 1.5 k ESD Machine model 200 V, 100 pF, 1.5 k latch-up 100 mA, 1.5 x VDD (absolute maximum) REQUIREMENTS(1) <15% LTPD <15% LTPD <15% LTPD
ESD and latch-up
Note to Tables 1 to 4 1. ppm = fraction of defective devices, in parts per million. LTPD = Lot Tolerance Percent Defective. FPM = fraction of devices failing at test condition, in Failures Per Million. FITS = Failures In Time Standard.
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9
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
CHARACTERISTICS VDD = 5 V 10%; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDD IDD(tot) Inputs CVBS Vsync td(sync) sync amplitude delay from CVBS to TCS output from STTV buffer (nominal video, average of leading/trailing edge) change in sync delay between all black and all white video input at nominal levels video input amplitude (peak-to-peak value) display PLL catching range Zsource Ci IREF Rgnd POL VIL VIH ILI Ci LFB VIL VIH ILI Ii td(LFB) VCR/FFB VIL VIH ILI Ii LOW level input voltage HIGH level input voltage input leakage current input current Vi = 0 to VDD note 1 -0.3 2.0 -10 -1 - - - - +0.8 +10 +1 LOW level input voltage HIGH level input voltage input leakage current input current delay between LFB front edge and input video line sync Vi = 0 to VDD note 1 -0.3 2.0 -10 -1 - - - - - 250 +0.8 +10 +1 - LOW level input voltage HIGH level input voltage input leakage current input capacitance Vi = 0 to VDD -0.3 2.0 -10 - - - - - +0.8 +10 10 resistor to ground - 27 - source impedance input capacitance 0.1 -150 0.3 0 0.6 +150 supply voltage total supply current 4.5 - 5.0 90 5.5 120 PARAMETER CONDITIONS MIN. TYP.
SAA5249
MAX.
UNIT
V mA
V ns
td(sync)
0
-
25
ns
Vvid(p-p)
0.7 7 - -
1.0 - - -
1.4 - 250 10
V % pF
k
V A pF
VDD + 0.5 V
V A mA ns
VDD + 0.5 V
V A mA
VDD + 0.5 V
1996 Nov 07
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SYMBOL RGBREF note 2 VIL ILI IDC VIL VIH ILI SCL VIL VIH ILI fSCL tr tf Ci LOW level input voltage HIGH level input voltage input leakage current clock frequency input rise time input fall time input capacitance 10% to 90% 90% to 10% Vi = 0 to VDD -0.3 3.0 -10 0 - - - - - - - - - - +1.5 +10 100 2 2 10 LOW level input voltage input leakage current DC current Vi = 0 to VDD -0.3 -10 - -0.3 2.0 Vi = 0 to VDD -10 - - - - - - PARAMETER CONDITIONS MIN. TYP.
SAA5249
MAX.
UNIT
VDD + 0.5 V +10 10 A mA
SEL1 AND SEL2 LOW level input voltage HIGH level input voltage input leakage current +0.8 +10 V A V A kHz s s pF VDD + 0.5 V
VDD + 0.5 V
Inputs/outputs CRYSTAL OSCILLATOR (OSCIN; OSCOUT) fXTAL Gv Gm Ci CFB BLACK Cblk ILI SDA VIL VIH ILI Ci tr tf VOL tf CL LOW level input voltage HIGH level input voltage input leakage current input capacitance input rise time input fall time LOW level output voltage output fall time load capacitance 10% to 90% 90% to 10% IOL = 3 mA 3 V to 1 V Vi = 0 to VDD -0.3 3.0 -10 - - - 0 - - - - - - - - - - - +1.5 +10 10 2 2 0.5 200 400 V A pF s s V ns pF VDD + 0.5 V storage capacitor to ground input leakage current Vi = 0 to VDD - -10 100 - - +10 nF A crystal frequency small signal voltage gain mutual conductance input capacitance feedback capacitance fi = 100 kHz - 3.5 1.5 - - 27 - - - - - - - 10 5 mA/V pF pF MHz
1996 Nov 07
11
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SYMBOL D0 TO D3 VIL VIH ILI Ci VOL VOH tr tf CL Outputs STTV Gstt VTCS VDCs IO CL VOL VOH CL tr tf VOL VOH CL tr tf gain of STTV relative to video input TCS amplitude DC shift between TCS output and nominal video output output drive current load capacitance 0.9 0.2 - - - IOL = +1.6 mA IOH = -0.2 mA 0.6 to 2.2 V 2.2 to 0.6 V 0 2.4 - - - 0 2.4 - 0.6 to 2.2 V 2.2 to 0.6 V - - 1.0 0.3 - - - - - - - - - - - - - 1.1 0.45 0.15 3.0 100 LOW level input voltage HIGH level input voltage input leakage current input capacitance LOW level output voltage HIGH level output voltage output rise time output fall time load capacitance IOL = +1.6 mA IOH = -0.2 mA 0.6 to 2.2 V 2.2 to 0.6 V -0.3 2.0 -10 - 0 2.4 - - - - - - - - - - - - +0.8 +10 10 0.4 VDD 20 20 50 PARAMETER CONDITIONS MIN. TYP.
SAA5249
MAX.
UNIT
V A pF V V ns ns pF
VDD + 0.5 V
V V mA pF
A0 TO A9 ADDRESS OUTPUT TO MEMORY A0 TO A9 LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.4 VDD 50 20 20 V V pF ns ns
R/W, CASO AND CAS1 LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time IOL = +1.6 mA IOH = -0.2 mA 0.4 VDD 50 20 20 V V pF ns ns
1996 Nov 07
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SYMBOL R, G AND B VOL VOH |Zo| CL IDC tr tf BLANK VOL VOH VOH VOH CL tr tf ODD/EVEN VOL VOH CL tr tf VOH VOL CL tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.6 to 2.2 V 2.2 to 0.6 V IOL = +1.6 mA IOH = -0.2 mA 0 2.4 - - - - IOL = 5 mA 0 - load resistor of 1.2 k - to VDD; measured between VDD - 0.5 V and 1.5 V Vi = 0 to VDD -10 - - - - - - - - - - 0.4 VDD 120 50 50 LOW level output voltage HIGH level output voltage HIGH level output voltage allowed voltage at pin load capacitance output rise time output fall time 10% to 90% 90% to 10% IOL = 1.6 mA IOH = -0.2 mA; VDD = 4.5 V IOH = 0 mA; VDD = 5.5 V with external pull-up 0 1.1 - - - - - - - - - - - - 0.4 - 2.8 VDD 50 20 20 LOW level output voltage HIGH level output voltage output impedance load capacitance DC current output rise time output fall time 10% to 90% 90% to 10% IOL = 2 mA 0 - RGBREF - - - - - 0.2 PARAMETER CONDITIONS MIN. TYP.
SAA5249
MAX.
UNIT
V V pF mA ns ns
IOH = -1.6 mA; RGBREF RGBREF VDD - 2 V -0.25 - - - - -
RGBREF +0.25 200 50 -3.3 20 20
V V V V pF ns ns
V V pF ns ns
COR AND Y (OPEN-DRAIN) pull-up voltage at pin output voltage LOW load capacitance output fall time VDD 1.0 25 50 V V pF ns
ILO tskew
output leakage current skew delay between display outputs R, G, B, COR, Y and BLANK
- -
+10 20
A ns
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SYMBOL Timing DRAM INTERFACE tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tDZO tr, tf tWCS tWCH tDS tDH tRAC tCAC tAA tRCS tRCH tRRH tRAL tOFF1 tCDD read or write cycle time RAS precharge time RAS pulse width CAS pulse width row address set-up time row address hold time column address set-up time column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time CAS set-up time from data input rise and fall times write set-up time write command hold time data input set-up time data input hold time access time from RAS access time from CAS access time from address read command set-up time read command hold time to CAS read command hold time to RAS column address to RAS lead time output buffer turn-off time CAS to data input delay time 344 125 194 113 30 50 50 50 130 60 15 260 60 200 10 193 116 193 42 165 0 95 193 0 55 90 20 25 380 140 210 133 60 60 60 60 148 74 60 286 70 225 15 212 137 212 62 183 35 108 212 10 65 133 30 35 415 155 230 153 80 92 75 70 160 105 70 300 80 280 20 235 150 235 80 220 40 120 235 20 100 150 40 45 PARAMETER CONDITIONS MIN. TYP.
SAA5249
MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Nov 07
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SYMBOL I2C-BUS tLOW tHIGH tSU;DAT tHD;DAT tSU;STO tBUF tHD;STA tSU;STA Notes clock LOW period clock HIGH period data set-up time data hold time set-up time from clock HIGH to STOP START set-up time following a STOP START hold time START set-up time following clock LOW-to-HIGH transition 4 4 250 170 4 4 4 4 - - - - - - - - - - - - - - - - PARAMETER CONDITIONS MIN. TYP.
SAA5249
MAX. s s ns ns s s s s
UNIT
1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs. Series current limiting resistors must be used to limit the input currents to 1 mA. 2. RGBREF is the positive supply pin for the RGB output pins and it must be able to source the IOH current from the R, G and B pins. The leakage specification on RGBREF only applies when there is no current load on the RGB pins.
1996 Nov 07
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Preliminary specification
SAA5249
Fig.4 Composite sync waveforms.
handbook, full pagewidth
1996 Nov 07
64 s 32 34.33 64 s 27.33 32 59.33 64 s
0
4.66
Philips Semiconductors
LSP (Line Sync Pulse)
0 2.33
EP (Equalizing Pulse)
0
Integrated VIP and Teletext with Background Memory Controller
BP (Broad Pulse)
621 (308) 622 (309) 1 2 3 4 5
623 (310)
624 (311)
625 (312)
16
310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 309 310 311 312 1 2 3 4 5
6
7
TCS interlaced
309
318 (5)
319 (6)
320 (7)
TCS interlaced
308
6
7
TCS non-interlaced
MLA037 - 2
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SAA5249
handbook, full pagewidth LSP
(TCS) 0 4.66 40 s R, G, B, Y (1) 0 16.67 display period 56.67 s 64 s
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) R, G, B, Y (1) 0 41 display period 312 291 line numbers
MLA662 - 1
(1) Also BLANK in character and box blanking.
Fig.5 Display output timing (a) line rate (b) field rate.
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL t HIGH t SU;DAT
t HD;STA
tr
t HD;DAT
SDA
MBC764
t SU;STA
t SU;STO
Fig.6 I2C-bus timing.
1996 Nov 07
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SAA5249
t RC t RAS RAS t RSH tf t RCD t CAS t CSH CAS t ASR t RAH ADDRESS ROW t RAD t ASC COLUMN t CAH t RCS WE t CAC t AA DATA OUTPUT high impedance t RRH t OFF1 DATA VALID t RCH t RAL t RP t CRP
t RAC t DZO DATA INPUT high impedance t CDD
MBA732
Fig.7 DRAM interface timing; read cycle.
1996 Nov 07
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Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SAA5249
t RC t RAS RAS t RSH tf t RCD t CAS t CSH CAS t ASR t RP t CRP
t RAH ROW
tASC COLUMN t CAH t WCS t WCH
ADDRESS
WE t DS
t DH DATA VALID
DATA INPUT
DATA OUTPUT
high impedance
MBA731
Fig.8 DRAM interface timing; write cycle.
1996 Nov 07
19
FIRST FIELD START (EVEN) 622 (309) 1 2 3 4 5 6 7 623 (310) 624 (311) 625 (312)
1996 Nov 07
2 s
621 (308)
Philips Semiconductors
TCS interlaced
ODD/EVEN output (normal sync mode)
Integrated VIP and Teletext with Background Memory Controller
ODD/EVEN output (normal sync mode when VCS to SCS mode active) 48 s
ODD/EVEN output (slave sync mode) 31 s
20
SECOND FIELD START (ODD) 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 2 s 16 s 31 s
309
318 (5)
319 (6)
320 (7)
TCS interlaced
ODD/EVEN output (normal sync mode)
ODD/EVEN output (normal sync mode when VCS to SCS mode active)
ODD/EVEN output (slave sync mode)
MBA073 - 4
Preliminary specification
SAA5249
Fig.9 ODD/EVEN timing.
KEY
1
D
KEY
1996 Nov 07
G 3 6 C1 C2 100 nF 33 F 12 V DD2 3 V DD1 4 5 B BLANKING ODD/EVEN +5 V
GND
R
Philips Semiconductors
X1
X3
1
2
IC1 SAA5249 IC2
1
+5 V
APPLICATION INFORMATION
KEY C13 100 nF
R1 10 k
VCR
2
CVBS C8 100 nF
3
C3 100 nF
+5 V
LK1 LINK
R2 1 k
STTV
4
Integrated VIP and Teletext with Background Memory Controller
C11 100 nF C12 10 F
X2
C7 1 nF 46 45 G1 27 MHz R9 27 k
LK2 LINK C5 8.2 pF C9 L1 100 nF 3.3 H
C4 100 nF
47 43 48 44 39 36 34 32 25 26 33 35 37 40 42 41 23 24 4 3 7 6 20 19 18 17 15 14 13 12 11 10 8 9 2 D3 15 D2 V CC D1 D0 5 A8 V SS A7 1 A6 OE A5 A4 A3 A2 A1 A0 A9 WE RAS CAS
1
IC3
R3 1 k
C7 R11 15 pF 3.3 k
21
C10 100 nF +5 V +5 V R5 4.7 k R6 4.7 k R7 220 R9 4.7 k R10 4.7 k R8 220 GND 2 SCL 3 SDA LK3 LINK LK4 LINK
27 28 21 19 18 17 29 15 10 14 9 20 16 13 4 5 8 7 6 11 30 31 22, 38 COR ODD/EVEN D3 BLANK D2 B D1 G D0 R A8 Y A7 VCR A6 CVBS A5 STTV A4 BLACK A3 RGBREF A2 VSS2 A1 POL A0 OSCOUT A9 OSCIN R/W REF + RAS V SS1 CAS0 GNDO CAS1 IREF SCL SEL1 SDA SEL2 VSS3 , VSS4
KEY
NOTE : FOR +VE GOING SYNC FIT LK1 FOR - VE GOING SYNC FIT LK2
2
3
+5 V
4 3 7 6 10 20 19 18 17 16 14 13 12
4
5
D3 15 D2 V CC C14 D1 100 D0 nF 5 A8 V SS A7 1 A6 OE A5 A4 A3 A2 C13 and C14 A1 are optional A0 surface mounted capacitors mounted 8 WE close to IC 9 RAS 2 CAS
n.c.
X4
LINK 34
MLB307
DRAM (120 nS) IC2 IC3 256K x 4 256K x 4 256K x 4 1M x 4 -
IC2 and IC3 pin-outs are for Dual In-Line Package (DIP)
Preliminary specification
SAA5249
Fig.10 Application diagram; 1 or 4 Mbit DRAM.
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
IVT1.1BMCX page memory organization
SAA5249
The organization of the page memory is illustrated by Fig.11. The IVT1.1BMCX provides an additional row as compared with first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the teletext page; Row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt information.
7 characters for status 7 1
fixed character written by IVT hardware alphanumerics white for normal alphanumerics green when looking for display page 24 24 characters from page header rolling when display page looked for
8 characters always rolling (time) 8
ROW 0 1 2 3 4
MAIN PAGE DISPLAY AREA
5 to 20
PACKET X / 22 PACKET X / 23 PACKET X / 24 STORED HERE IF R0D7 = 1 10 14 10 bytes for received page information 14 bytes free for use by microcontroller
21 22 23 24 25
MBA274
Fig.11 Basic page memory organization.
REMARK TO Fig.11
Row 0
ROW PACKET X / 24 if R0D7 = 0 PACKET X / 27 / 0 PACKETS 8 / 30 / 0 to 15
MBA275 - 2
0 1 2
Row 0 is for the page header. The first seven columns (0 to 6) are free for status messages. The eighth is an alphanumeric white or green control character, written automatically by IVT1.1BMCX to give a green rolling header when a page is being looked for. The last eight characters are for rolling time.
Row 25
The first 10 bytes of row 25 contain control data relating to the received page as shown in Table 5. The remaining 14-bytes are free for use by the microcomputer.
Fig.12 Organization of the extension memory.
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22
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 5 D0 D1 D2 D3 D4 D5 D6 D7 Column Table 6 Row 25 received control data format PU0 PU1 PU2 PU3 0 0 0 0 PT0 PT1 PT2 PT3 0 0 0 1 MU0 MU1 MU2 MU3 0 0 0 2 MT0 MT1 MT2 C4 0 0 0 3 HU0 HU1 HU2 HU3 0 0 0 4 HT0 HT1 C5 C6 0 0 0 5 C7 C8 C9 C10 0 0 0 6 C11 C12 C13 C14 0 0 0 7
SAA5249
MAG0 MAG1 MAG2 0 0 0 0 8
0 0 0 0 0 PBLF 0 0 9
HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND
Page number and sub-code for Table 5
Page number MAG PU PT PBLF FOUND HAM.ER Page sub-code MU MT HU HT C4 to C14 minutes units minutes tens hours units hours tens transmitted control bits magazine page units page tens page being looked for LOW for page has been found hamming error in corresponding byte
1996 Nov 07
23
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Register maps
SAA5249
IVT1.1BMCX mode registers R0 to R11 are shown in Table 7. R0 to R10 are write only; R11 is read/write. Register map (R3), for page requests, is shown in detail in Table 9. Table 7 Register map (notes 1 to 5) D7 D6 D5 AUTO ODD/ EVEN ACQ ON/OFF - D4 DISABLE HDR ROLL DISABLE PKT 26 - D3 DISPLAY SRATUS ROW ONLY DEW/ FULL FIELD TB D2 DISABLE ODD/ EVEN TCS ON - D1 D0 R11/R11B SELECT
REGISTER Adv. control 0
X24 POS FREE RUN PLL
Mode
1
VCS TO SCS -
7 + P/ 8-BIT -
T1
T0
Page request address Page request data Display control (normal) Display control (newsflash /subtitle) Display mode
2
START START START COLUMN COLUMN COLUMN SC2 SC1 SC0 PRD2 PRD1 PRD0
3
-
-
CLEAR B.M. -
PRD4
PRD3
- 5 BKGND OUT BKGND OUT
-
-
-
-
-
-
BKGND IN COR OUT COR IN
TEXT OUT TEXT IN
PON OUT PON IN
6
BKGND IN COR OUT COR IN
TEXT OUT TEXT IN
PON OUT PON IN
7
STATUS CURSOR BTM ON TOP - - CLEAR MEM. - D6 ROM VER R4 - - D7
CONCEA TOP/BTM L REVEAL HALF ON - A0 C5 D5 ROM VER R3 - R4 C4 D4 ROM VER R2
SINGLE DOUBLE HEIGHT - R3 C3 D3 ROM VER R1
BOX ON 24 - R2 C2 D2 ROM VER R0
BOX ON 1-23 - R1 C1 D1 TEXT SIGNAL QUALITY
BOX ON 0
- R0 C0 D0 VCS SIGNAL QUALITY
Cursor row Cursor column Device status
9 10
Cursor data 11
11B 625/525 SYNC
1996 Nov 07
24
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Notes
SAA5249
1. The dash (-) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. All bits in registers R0 to R10 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6 which are set to logic 1. 3. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white (00000111) as the acquisition circuit is enabled but the page is on hold. 4. TB must be set to logic 0 for normal operation. 5. The I2C-bus slave address is 0010001. Table 8 Register description
R0 ADVANCED CONTROL - auto increments to register 1 R11/R11B SELECT DISABLE ODD/EVEN DISPLAY STATUS ROW selects reading of R11 or R11B forces ODD/EVEN output LOW when logic 1 when SET = 1 and R1D6 = 1 open (8-bit mode) then all the text display is blanked out apart from the status row, this allows the page memory to be used for non-textural data, such as in the German TOP system disables green rolling header and time when set forces ODD/EVEN LOW if any TV picture displayed, if DISABLE ODD/EVEN = 0 will force the PLL to free run in all conditions automatic display of FASTEXT prompt row when logic 1
DISABLE HDR ROLL AUTO ODD/EVEN FREE RUN PLL X24 POS
R1 MODE - auto increments to register 2 T0, T1 TCS ON DEW/FULL FIELD DISABLE PKT 26 ACQ ON/OFF 7 + P/8-BIT VCS TO SCS interlace/non-interlace 312/313 line control (see Table 10) text composite sync or direct sync select (see Table 10 for FFB mode selection) field-flyback or full-channel mode disable automatic processing of packet 26 acquisition circuits turned off when logic 1 7-bits with parity checking or 8-bit mode when logic 1 enables display of messages with 60 Hz input signal
R2 PAGE REQUEST ADDRESS - auto increments to register 3 COL SCO - SC2 TB point to start column for page request data (see Table 9) must be logic 0 for normal operation
R3 PAGE REQUEST DATA - does not auto increment (see Table 9) CLEAR B.M. when set to logic 1. Useful when transmission channel changes
R5 NORMAL DISPLAY CONTROL - auto increments to register 6 R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto increments to register 7; (note 1) PON TEXT COR BKGND picture on text on contrast reduction on background colour on
1996 Nov 07
25
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
R7 DISPLAY MODE - does not auto increment BOX ON 0 BOX ON 1-23 BOX ON 24 DOUBLE HEIGHT BOTTOM HALF REVEAL ON CURSOR ON STATUS TOP boxing function allowed on Row 0 boxing function allowed on Rows 1 to 23 boxing function allowed on Row 24 to display double height text to select bottom half of page when DOUBLE HEIGHT = 1 to reveal concealed text to display cursor row 25 displayed above or below the main text active row for data written to or read from memory via the I2C-bus
SAA5249
R9 CURSOR ROW - auto increments to register 10 R0 to R4 A0 CLEAR MEM. selects display memory page (when = 0) or extension packet memory (when = 1) when set to 1, clears the display memory; this bit is automatically reset active column for data written to or read from memory via the I2C-bus data read from/written to memory via I2C-bus, at location pointed to by R9 and R10. This location automatically increments each time R11 is accessed
R10 CURSOR COLUMN - auto increments to register 11 or 11B C0 to C5
R11 CURSOR DATA - does not auto increment D0 to D7
R11B DEVICE STATUS - does not auto increment VCS SIGNAL QUALITY TEXT SIGNAL QUALITY ROM VER R0 to R4 625/525 SYNC Note 1. These functions have IN and OUT referring to inside and outside the boxing function respectively. indicates that the video signal quality is good and PLL is phase locked to input video when = 1 if a good teletext signal is being received when logic 1 indicated language/ROM variant. For Western European = 11 000 if the input video is a 525 line signal when logic 1
1996 Nov 07
26
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 9 Register map for page requests (R3); notes 1 to 5 PRD4 DO CARE magazine 1 2 3 4 5 6 DO CARE page tens DO CARE page units DO CARE hours tens DO CARE hours units DO CARE minutes tens DO CARE minutes units Notes 1. Abbreviations are as for Table 5 except for DO CARE bits. MU3 MU2 MU1 X MT2 MT1 HU3 HU2 HU1 X X HT1 PU3 PU2 PU1 PT3 PT2 PT1 HOLD MAG2 MAG1 PRD3 PRD2 PRD1
SAA5249
START COLUMN 0
PRD0 MAG0 PT0 PU0 HT0 HU0 MT0 MU0
2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page selection. 3. If HOLD is set LOW, the page is held and not updated. 4. Columns auto-increment on successive I2C-bus transmission bytes. 5. X = don't care. Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option; notes 1 and 2 TCS ON FFB MODE X X X 0 1 Notes 1. Reverts to interlaced mode if a newsflash or subtitle is being displayed. 2. X = Don't care. T1 0 0 1 1 1 T0 0 1 0 1 1 interlaced 312.5/312.5 lines non-interlaced 312/313 lines (note 1) non-interlaced 312/313 lines (note 1) SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field RESULT
1996 Nov 07
27
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
CLOCK SYSTEMS Crystal oscillator
SAA5249
The crystal is a conventional 2-pin design operating at 27 MHz. It is capable of oscillating with both fundamental and third overtone mode crystals. External components should be used to suppress the fundamental output of the third overtone as illustrated in Fig.13.
VDD1
3 (25)
SAA5249
OSCOUT 15 pF 8.2 pF 100 nF 1 nF 3.3 H 27 MHz 3rd overtone OSCIN
4 (27) CRYSTAL OSCILLATOR 5 (28)
3.3 k
GNDO
6 (29)
MLB308
Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT319-1.
Table 11 Crystal characteristics (see Fig.13) SYMBOL PARAMETER - - - - - - - - MIN. TYP. - - - 50 - 5 25 25 MAX. UNIT
Crystal (27 MHz, 3rd overtone) C1 C0 CL Rr R1 Xa Xj Xd series capacitance parallel capacitance load capacitance resonance resistance series resistance ageing adjustment tolerance drift 1.7 5.2 20 - 20 - - - pF pF pF 10-6/year 10-6 10-6
1996 Nov 07
28
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
CHARACTER SETS
SAA5249
The WST specification allows the selection of national character sets via the page header transmission bits, C12 to C14. The basic 96 character sets differ only in 13 national option characters as indicated in the Tables 16, 17 and 18 with reference to their table position in the basic character matrix illustrated in Table 15. The IVT1.1BMCX automatically decodes transmission bits C12 to C14. Tables 12, 13 and 14 illustrate the character matrixes. Character bytes are listed as transmitted from b1 to b7.
MLA663 handbook, full pagewidth
alphanumerics and graphics 'space' character 0000010
alphanumerics character 1011010
alphanumerics or blast-through alphanumerics character 0001001
alphanumerics character 1111111
contiguous graphics character 0110111
separated graphics character 0110111 =
separated graphics character 1111111 background colour
contiguous graphics character 1111111 display = colour
Fig.14 Character format.
1996 Nov 07
29
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 12 SAA5249P/E character data input decoding, West European languages; notes 1 to 9 For character version number (11000) see Register 11B.
b8 B handbook, full pagewidth I T S b7 b6 b5 b 4 b 3 b2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 1 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1
SAA5249
1 1 0 1 14 1 0
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
0
1
1
0
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
(1)
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
ESC
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MBA429
1996 Nov 07
30
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 13 SAA5249P/H character data input decoding, West European languages; notes 1 to 9 For character version number (11001) see Register 11B.
handbook, full pagewidth B b8
I T S b7 b6 b5 b 4 b 3 b 2 b 1 r o w 0 0 0 0 0 column 0
SAA5249
0 0 0 0
0 0 0 1 1 graphics black graphics red graphics green
0 or 1 0 1 0 2
0 0 1 0 2a
0 or 1 0 1 1 3
0 0 1 1 3a
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6 6a
0 1 1 1 7 7a
1 0 0 0 8
1 0 0 1 9
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
0
1
1
0
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
(1)
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
ESC
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MLA961
1996 Nov 07
31
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SAA5249
Table 14 SAA5249P/T character data input decoding, West European and Turkish languages; notes 1 to 9 For character version number (11010) see Register 11B.
handbook, full pagewidth b8 B
I T S b7 b6 b5 b 4 b 3 b2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 1 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
0
1
1
0
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
(1)
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
ESC
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MBA431
1996 Nov 07
32
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 15 SAA5249P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9 For character version number (11101) see Register 11B.
B I T S b8 b7 b6 b5 b 4 b 3 b 2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green graphics yellow 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 1 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1 0
SAA5249
1 1 1 1 14 0
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
handbook, full pagewidth 0 011
6
graphics cyan
0
1
1
1
7
graphics white conceal display
(2)
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
TWIST
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MBA648 - 1
1996 Nov 07
33
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Notes to Tables 12, 13, 14 and 15 1. These control characters are reserved for compatibility with other data codes. 2. These control characters are presumed before each row begins. 3. Control characters shown in Columns 0 and 1 are normally displayed as spaces. 4. Characters may be referred to by column and row (for example 2/5 refers to %). 5. Black represents displayed colour. White represents background. 6. The SAA5249 national option characters are illustrated in Tables 16, 17,18 and 19. 7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5 (E, H and T codes only).
SAA5249
8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped into the basic code table into positions shown in Tables 16, 17, 18 and 19. 9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.
1996 Nov 07
34
SAA5249
Note
Preliminary specification
1. Where: NC = national option character position.
full pagewidth
1996 Nov 07
3/8 6/0 NC NC 4/0 4/8 5/0 5/8 6/8 7/0 7/8 3/9 4/1 4/9 5/1 5/9 6/1 6/9 7/1 7/9 3/10 4/2 4/10 5/2 5/10 6/2 6/10 7/2 7/10
Table 16 SAA5249 basic character matrix; note 1
Philips Semiconductors
2/0
2/8
3/0
2/1
2/9
3/1
2/2
2/10
3/2
Integrated VIP and Teletext with Background Memory Controller
2/3 3/11 5/11 NC 4/3 4/11 5/3 6/3 6/11 7/3
2/11
3/3
7/11 NC
NC
2/4 3/12 NC 4/4 4/12 5/4 6/4 6/12
2/12
3/4
5/12
7/4
7/12 NC
35
3/13 NC 4/5 4/13 5/5 5/13 6/5 6/13 3/14 4/6 4/14 5/6 5/14 NC 6/6 3/15 4/7 4/15 5/7 5/15 NC 6/7 6/15
NC
2/5
2/13
3/5
7/5
7/13 NC
2/6
2/14
3/6
7/6
7/14 NC
2/7
2/15
3/7
7/7
7/15
MLA630
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 17 SAA5249P/E national option character set; note 1
handbook, full pagewidth
(1)
SAA5249
PHCB
CHARACTER POSITION (COLUMN / ROW) 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14
LANGUAGE C12 C13 C14 2 / 3 ENGLISH 0 0 0
GERMAN
0
0
1
SWEDISH
0
1
0
ITALIAN
0
1
1
FRENCH
1
0
0
SPANISH
1
0
1
MLB458
Note 1. PHCB are the Page Header Control Bits. Other combinations default to English.
1996 Nov 07
36
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 18 SAA5249P/H national option character set; note 1
handbook, full pagewidth
(1)
SAA5249
PHCB
CHARACTER POSITION (COLUMN / ROW) 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14
LANGUAGE C12 C13 C14 2 / 3 POLISH 0 0 0
GERMAN
0
0
1
SWEDISH
0
1
0
SERBO-CROAT
1
0
1
CZECHOSLOVAKIA
1
1
0
RUMANIAN
1
1
1
MLA966
Note 1. PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change with the PHCB. All other characters in the basic set are shown in Table 15.
1996 Nov 07
37
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
Table 19 SAA5249P/R national option character set; note 1
handbook, full pagewidth
SAA5249
PHCB
(1)
CHARACTER POSITION (COLUMN / ROW) 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14
LANGUAGE C12 C13 C14 2 / 3 ESTONIAN LETTISH / LITHUANIAN RUSSIAN 0 1 0
0
1
1
1
0
0
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MEA597
Note 1. PHCB are the Page Header Control Bits. Other combinations default to Estonian. 1996 Nov 07 38
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
PACKAGE OUTLINES DIP48: plastic dual in-line package; 48 leads (600 mil)
SAA5249
SOT240-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 48 25 MH wM (e 1)
pin 1 index E
1
24
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.9 0.19 A1 min. 0.36 0.014 A2 max. 4.06 0.16 b 1.4 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 62.60 61.60 2.46 2.42 E (1) 14.22 13.56 0.56 0.53 e 2.54 0.10 e1 15.24 0.60 L 3.90 3.05 0.15 0.12 ME 15.88 15.24 0.63 0.60 MH 18.46 15.24 0.73 0.60 w 0.254 0.01 Z (1) max. 2.1 0.083
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT240-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-25
1996 Nov 07
39
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SAA5249
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT319-1
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
wM pin 1 index bp 64 1 wM D HD ZD B vM B 19 vM A 20
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.50 0.35 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.43 1.23 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Nov 07
40
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. QFP REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1996 Nov 07 41
SAA5249
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5249
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 07
42
Philips Semiconductors
Preliminary specification
Integrated VIP and Teletext with Background Memory Controller
NOTES
SAA5249
1996 Nov 07
43
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/50/02/pp44
Date of release: 1996 Nov 07
Document order number:
9397 750 01014

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